Integrated circuit having contact including material between sidewalls

ABSTRACT

An integrated circuit includes a bottom electrode, a top electrode, resistivity changing material between the bottom electrode and the top electrode, and a contact contacting the top electrode. The contact includes a bottom and sidewalls. The integrated circuit includes first material between the sidewalls of the contact.

BACKGROUND

One type of memory is resistive memory. Resistive memory utilizes theresistance value of a memory element to store one or more bits of data.For example, a memory element programmed to have a high resistance valuemay represent a logic “1” data bit value and a memory element programmedto have a low resistance value may represent a logic “0” data bit value.Typically, the resistance value of the memory element is switchedelectrically by applying a voltage pulse or a current pulse to thememory element.

One type of resistive memory is phase change memory. Phase change memoryuses a phase change material in the resistive memory element. The phasechange material exhibits at least two different states. The states ofthe phase change material may be referred to as the amorphous state andthe crystalline state, where the amorphous state involves a moredisordered atomic structure and the crystalline state involves a moreordered lattice. The amorphous state usually exhibits higher resistivitythan the crystalline state. Also, some phase change materials exhibitmultiple crystalline states, e.g. a face-centered cubic (FCC) state anda hexagonal closest packing (HCP) state, which have differentresistivities and may be used to store bits of data. In the followingdescription, the amorphous state generally refers to the state havingthe higher resistivity and the crystalline state generally refers to thestate having the lower resistivity.

Phase changes in the phase change materials may be induced reversibly.In this way, the memory may change from the amorphous state to thecrystalline state and from the crystalline state to the amorphous statein response to temperature changes. The temperature changes to the phasechange material may be achieved by driving current through the phasechange material itself or by driving current through a resistive heateradjacent the phase change material. With both of these methods,controllable heating of the phase change material causes controllablephase change within the phase change material.

A phase change memory including a memory array having a plurality ofmemory cells that are made of phase change material may be programmed tostore data utilizing the memory states of the phase change material. Oneway to read and write data in such a phase change memory device is tocontrol a current and/or a voltage pulse that is applied to the phasechange material. The level of current and/or voltage generallycorresponds to the temperature induced within the phase change materialin each memory cell.

To achieve higher density phase change memories, a phase change memorycell can store multiple bits of data. Multi-bit storage in a phasechange memory cell can be achieved by programming the phase changematerial to have intermediate resistance values or states, where themulti-bit or multilevel phase change memory cell can be written to morethan two states. If the phase change memory cell is programmed to one ofthree different resistance levels, 1.5 bits of data per cell can bestored. If the phase change memory cell is programmed to one of fourdifferent resistance levels, two bits of data per cell can be stored,and so on. To program a phase change memory cell to an intermediateresistance value, the amount of crystalline material coexisting withamorphous material and hence the cell resistance is controlled via asuitable write strategy.

One type of phase change memory cell includes phase change materialbetween a bottom electrode and a top electrode. A contact couples thetop electrode to upper metallization layers. To reduce the power used toprogram the phase change material to an amorphous state, heat loss fromthe phase change material during programming should be minimized.

For these and other reasons, there is a need for the present invention.

SUMMARY

One embodiment provides an integrated circuit. The integrated circuitincludes a bottom electrode, a top electrode, resistivity changingmaterial between the bottom electrode and the top electrode, and acontact contacting the top electrode. The contact includes a bottom andsidewalls. The integrated circuit includes first material between thesidewalls of the contact.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 is a block diagram illustrating one embodiment of a system.

FIG. 2 is a diagram illustrating one embodiment of a memory device.

FIG. 3 illustrates a cross-sectional view of one embodiment of a phasechange element.

FIG. 4 illustrates a cross-sectional view of another embodiment of aphase change element.

FIG. 5 illustrates a top view of one embodiment of a contact.

FIG. 6 illustrates a top view of another embodiment of a contact.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments of the present invention can be positioned ina number of different orientations, the directional terminology is usedfor purposes of illustration and is in no way limiting. It is to beunderstood that other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. The following detailed description, therefore, is notto be taken in a limiting sense, and the scope of the present inventionis defined by the appended claims.

FIG. 1 is a block diagram illustrating one embodiment of a system 90.System 90 includes a host 92 and a memory device 100. Host 92 iscommunicatively coupled to memory device 100 through communication link94. Host 92 includes a computer (e.g., desktop, laptop, handheld),portable electronic device (e.g., cellular phone, personal digitalassistant (PDA), MP3 player, video player), or any other suitable devicethat uses memory. Memory device 100 provides memory for host 92. In oneembodiment, memory device 100 includes a phase change memory device orother suitable resistive or resistivity changing material memory device.

FIG. 2 is a diagram illustrating one embodiment of memory device 100. Inone embodiment, memory device 100 is an integrated circuit or part of anintegrated circuit. Memory device 100 includes write circuit 124,controller 120, memory array 101, and sense circuit 126. Memory array101 includes a plurality of phase change memory cells 104 a-104 d(collectively referred to as phase change memory cells 104), a pluralityof bit lines (BLs) 112 a-112 b (collectively referred to as bit lines112), and a plurality of word lines (WLs) 110 a-110 b (collectivelyreferred to as word lines 110).

Each phase change memory cell 104 includes a cup-shaped or U-shapedcontact for reducing heat loss from the phase change material withineach memory cell 104 during programming. The bottom and sidewalls ofeach contact includes an electrically conductive material. A dielectricmaterial or semiconducting material having low thermal conductively isdisposed between the sidewalls of each contact.

As used herein, the term “electrically coupled” is not meant to meanthat the elements must be directly coupled together and interveningelements may be provided between the “electrically coupled” elements.

Memory array 101 is electrically coupled to write circuit 124 throughsignal path 125, to controller 120 through signal path 121, and to sensecircuit 126 through signal path 127. Controller 120 is electricallycoupled to write circuit 124 through signal path 128 and to sensecircuit 126 through signal path 130. Each phase change memory cell 104is electrically coupled to a word line 110, a bit line 112, and a commonor ground 114. Phase change memory cell 104 a is electrically coupled tobit line 112 a, word line 110 a, and common or ground 114, and phasechange memory cell 104 b is electrically coupled to bit line 112 a, wordline 110 b, and common or ground 114. Phase change memory cell 104 c iselectrically coupled to bit line 112 b, word line 110 a, and common orground 114, and phase change memory cell 104 d is electrically coupledto bit line 112 b, word line 110 b, and common or ground 114.

Each phase change memory cell 104 includes a phase change element 106and a transistor 108. While transistor 108 is a field-effect transistor(FET) in the illustrated embodiment, in other embodiments, transistor108 can be another suitable device such as a bipolar transistor or a 3Dtransistor structure. In other embodiments, a diode-like structure maybe used in place of transistor 108. Phase change memory cell 104 aincludes phase change element 106 a and transistor 108 a. One side ofphase change element 106 a is electrically coupled to bit line 112 a,and the other side of phase change element 106 a is electrically coupledto one side of the source-drain path of transistor 108 a. The other sideof the source-drain path of transistor 108 a is electrically coupled tocommon or ground 114. The gate of transistor 108 a is electricallycoupled to word line 110 a.

Phase change memory cell 104 b includes phase change element 106 b andtransistor 108 b. One side of phase change element 106 b is electricallycoupled to bit line 112 a, and the other side of phase change element106 b is electrically coupled to one side of the source-drain path oftransistor 108 b. The other side of the source-drain path of transistor108 b is electrically coupled to common or ground 114. The gate oftransistor 108 b is electrically coupled to word line 110 b.

Phase change memory cell 104 c includes phase change element 106 c andtransistor 108 c. One side of phase change element 106 c is electricallycoupled to bit line 112 b and the other side of phase change element 106c is electrically coupled to one side of the source-drain path oftransistor 108 c. The other side of the source-drain path of transistor108 c is electrically coupled to common or ground 114. The gate oftransistor 108 c is electrically coupled to word line 110 a.

Phase change memory cell 104 d includes phase change element 106 d andtransistor 108 d. One side of phase change element 106 d is electricallycoupled to bit line 112 b and the other side of phase change element 106d is electrically coupled to one side of the source-drain path oftransistor 108 d. The other side of the source-drain path of transistor108 d is electrically coupled to common or ground 114. The gate oftransistor 108 d is electrically coupled to word line 110 b.

In another embodiment, each phase change element 106 is electricallycoupled to a common or ground 114 and each transistor 108 iselectrically coupled to a bit line 112. For example, for phase changememory cell 104 a, one side of phase change element 106 a iselectrically coupled to common or ground 114. The other side of phasechange element 106 a is electrically coupled to one side of thesource-drain path of transistor 108 a. The other side of thesource-drain path of transistor 108 a is electrically coupled to bitline 112 a.

Each phase change element 106 comprises a phase change material that maybe made up of a variety of materials in accordance with the presentinvention. Generally, chalcogenide alloys that contain one or moreelements from group VI of the periodic table are useful as suchmaterials. In one embodiment, the phase change material of phase changeelement 106 is made up of a chalcogenide compound material, such asGeSbTe, SbTe, GeTe or AgInSbTe. In another embodiment, the phase changematerial is chalcogen free, such as GeSb, GaSb, InSb, or GeGaInSb. Inother embodiments, the phase change material is made up of any suitablematerial including one or more of the elements Ge, Sb, Te, Ga, As, In,Se, and S.

Each phase change element 106 may be changed from an amorphous state toa crystalline state or from a crystalline state to an amorphous stateunder the influence of temperature change. The amount of crystallinematerial coexisting with amorphous material in the phase change materialof one of the phase change elements 106 a-106 d thereby defines two ormore states for storing data within memory device 100. In the amorphousstate, a phase change material exhibits significantly higher resistivitythan in the crystalline state. Therefore, the two or more states ofphase change elements 106 a-106 d differ in their electricalresistivity. In one embodiment, the two or more states are two statesand a binary system is used, wherein the two states are assigned bitvalues of “0” and “1”. In another embodiment, the two or more states canbe three states and a ternary system can be used, wherein the threestates are assigned bit values of “0”, “1”, and “2”. In anotherembodiment, the two or more states are four states that can be assignedmulti-bit values, such as “00”, “01”, “10”, and “11”. In otherembodiments, the two or more states can be any suitable number of statesin the phase change material of a phase change element.

Controller 120 includes a microprocessor, microcontroller, or othersuitable logic circuitry for controlling the operation of memory device100. Controller 120 controls read and write operations of memory device100 including the application of control and data signals to memoryarray 101 through write circuit 124 and sense circuit 126. In oneembodiment, write circuit 124 provides voltage pulses through signalpath 125 and bit lines 112 to memory cells 104 to program the memorycells. In other embodiments, write circuit 124 provides current pulsesthrough signal path 125 and bit lines 112 to memory cells 104 to programthe memory cells.

Sense circuit 126 reads each of the two or more states of memory cells104 through bit lines 112 and signal path 127. In one embodiment, toread the resistance of one of the memory cells 104, sense circuit 126provides current that flows through one of the memory cells 104. Sensecircuit 126 then reads the voltage across that one of the memory cells104. In one embodiment, sense circuit 126 provides voltage across one ofthe memory cells 104 and reads the current that flows through that oneof the memory cells 104. In one embodiment, write circuit 124 providesvoltage across one of the memory cells 104 and sense circuit 126 readsthe current that flows through that one of the memory cells 104. In oneembodiment, write circuit 124 provides current that flows through one ofthe memory cells 104 and sense circuit 126 reads the voltage across thatone of the memory cells 104.

During a set operation of phase change memory cell 104 a, one or moreset current or voltage pulses are selectively enabled by write circuit124 and sent through bit line 112 a to phase change element 106 athereby heating phase change element 106 a above its crystallizationtemperature (but usually below its melting temperature) with word line110 a selected to activate transistor 108 a. In this way, phase changeelement 106 a reaches its crystalline state or a partially crystallineand partially amorphous state during this set operation.

During a reset operation of phase change memory cell 104 a, a resetcurrent or voltage pulse is selectively enabled by write circuit 124 andsent through bit line 112 a to phase change element 106 a. The resetcurrent or voltage quickly heats phase change element 106 a above itsmelting temperature. After the current or voltage pulse is turned off,phase change element 106 a quickly quench cools into the amorphous stateor a partially amorphous and partially crystalline state. Phase changememory cells 104 b-104 d and other phase change memory cells 104 inmemory array 101 are set and reset similarly to phase change memory cell104 a using a similar current or voltage pulse.

FIG. 3 illustrates a cross-sectional view of one embodiment of a phasechange element 200 a. In one embodiment, each phase change element 106is similar to phase change element 200 a. Phase change element 200 aincludes a bottom electrode 202, a phase change material storagelocation 204, a top electrode 206, a contact 208, dielectric orsemiconducting material 211, and dielectric material 210. In oneembodiment, phase change material storage location 204 is a mushroomphase change material storage location. In this embodiment, phase changematerial storage location 204 is formed by depositing and patterning alayer of phase change material over bottom electrode 202. Contact 208includes a bottom portion 212 and sidewall portions 214.

Bottom electrode 202 includes TiN, TaN, W, Al, Ti, Ta, TiSiN, TaSiN,TiAlN, TaAlN, Cu, WN, C, or other suitable electrode material. The topof bottom electrode 202 contacts the bottom of phase change materialstorage location 204. In one embodiment, phase change material storagelocation 204 has a larger cross-sectional width than bottom electrode202. Phase change material storage location 204 provides a storagelocation for storing one or more bits of data. The active or phasechange region in phase change material storage location 204 is at theinterface between phase change material storage location 204 and bottomelectrode 202. The top of phase change material storage location 204contacts the bottom of top electrode 206. In one embodiment, topelectrode 206 has the same cross-sectional width as phase changematerial storage location 204. Top electrode 206 includes TiN, TaN, W,Al, Ti, Ta, TiSiN, TaSiN, TiAlN, Cu, WN, C, or other suitable electrodematerial.

The top of top electrode 206 contacts the bottom 212 of contact 208. Inone embodiment, the bottom 212 of contact 208 has a smallercross-sectional width than top electrode 206. Contact 208 includes TiN,TaN, TiSiN, TaSiN, TiAlN, WN, or other suitable contact material. In oneembodiment, bottom portion 218 and sidewall portions 214 of contact 208provide a cup-shaped contact. In another embodiment, bottom portion 218and sidewall portions 214 of contact 208 provide a U-shaped contact. Inone embodiment, U-shaped contact 208 contacts at least two topelectrodes 206 along a row or column of memory array 101. In anotherembodiment, U-shaped contact 208, top electrode 206, and phase changematerial 204 extend over two or more bottom electrodes 202 along a rowor column of memory array 101 to provide multiple phase change elements.

In any embodiment, sidewall portions 214 laterally enclose dielectric orsemiconducting material 211. Dielectric or semiconducting material 211includes SiO₂, SiO_(x), SiN, fluorinated silica glass (FSG),boro-phosphorous silicate glass (BPSG), boro-silicate glass (BSG), low-kmaterial, or other suitable dielectric material or semiconductingmaterial. Bottom electrode 202, phase change material 204, top electrode206, and contact 208 are laterally surrounded by dielectric material210. Dielectric material 210 includes SiO₂, SiO_(x), SiN, FSG, BPSG,BSG, or other suitable dielectric material.

The current path through memory element 200 a is from contact 208through top electrode 206 and phase change material storage location 204to bottom electrode 202. In another embodiment, the current path isreversed. The heat loss within phase change element 200 a during aprogramming operation is indicated by arrows 220 extending away fromphase change material storage location 204. Compared to a typicalcontact including a solid block of material, cup-shaped or U-shapedcontact 208 reduces the heat loss in the upper direction due to therelatively thin bottom portion 212 that is covered with dielectric orsemiconducting material 211. Contact 208 reduces the heat loss fromphase change material storage location 204 during programming, thusreducing the power used to program phase change element 200 a.

During operation, current or voltage pulses are applied between contact208 and bottom electrode 202 to program phase change element 200 a.During a set operation of phase change element 200 a, a set current orvoltage pulse is selectively enabled by write circuit 124 and sentthrough a bit line to contact 208. From contact 208, the set current orvoltage pulse passes through top electrode 206 and phase change materialstorage location 204 thereby heating the phase change material above itscrystallization temperature (but usually below its melting temperature).In this way, the phase change material reaches a crystalline state or apartially crystalline and partially amorphous state during the setoperation.

During a reset operation of phase change element 200 a, a reset currentor voltage pulse is selectively enabled by write circuit 124 and sentthrough a bit line to contact 208. From contact 208, the reset currentor voltage pulse passes through top electrode 206 and phase changematerial storage location 204. The reset current or voltage quicklyheats the phase change material above its melting temperature. After thecurrent or voltage pulse is turned off, the phase change materialquickly quench cools into an amorphous state or a partially amorphousand partially crystalline state.

FIG. 4 illustrates a cross-sectional view of another embodiment of aphase change element 200 b. In one embodiment, each phase change element106 is similar to phase change element 200 b. Phase change element 200 bis similar to phase change element 200 a previously described andillustrated with reference to FIG. 3, except that in phase changeelement 200 b, phase change material storage location 204 includes afirst portion 216 and a second portion 218. In one embodiment, phasechange material storage location 204 is a pore phase change materialstorage location. In this embodiment, phase change material storagelocation 204 is formed by depositing phase change material into a poredefined in dielectric material 210.

In this embodiment, the first portion 216 of phase change material 204is tapered such that at the interface between phase change material 204and bottom electrode 202, phase change material 204 has a smallercross-sectional width than bottom electrode 202. In one embodiment,second portion 218 of phase change material 204 has the samecross-sectional width as top electrode 206. Phase change element 200 bis programmed similarly to phase change element 200 a previouslydescribed and illustrated with reference to FIG. 3.

FIG. 5 illustrates a top view of one embodiment of a contact 208 a. Inone embodiment, contact 208 a is used for contact 208 in phase changeelement 200 a previously described and illustrated with reference toFIG. 3 and in phase change element 200 b previously described andillustrated with reference to FIG. 4. In this embodiment, contact 208 ahas a circular or ring shaped cross-section. Contact 208 a enclosesdielectric or semiconducting material 211.

FIG. 6 illustrates a top view of another embodiment of a contact 208 b.In one embodiment, contact 208 b is used for contact 208 in phase changeelement 200 a previously described and illustrated with reference toFIG. 3 and in phase change element 200 b previously described andillustrated with reference to FIG. 4. In this embodiment, contact 208 bhas an elliptical or oblong shaped cross-section. Contact 208 b enclosesdielectric or semiconducting material 211. In other embodiments, square,rectangular, polygonal, or other suitable shapes can be used for contact208.

After fabricating top electrode 206, contact 208 is fabricated. Tofabricate contact 208, a first dielectric material, such as SiO₂,SiO_(x), SiN, FSG, BPSG, BSG, or other suitable dielectric material isdeposited over top electrode 206 to provide a first dielectric materiallayer. The first dielectric material layer is deposited using chemicalvapor deposition (CVD), high density plasma-chemical vapor deposition(HDP-CVD), atomic layer deposition (ALD), metal organic chemical vapordeposition (MOCVD), physical vapor deposition (PVD), jet vapordeposition (JVD), or other suitable deposition technique. The firstdielectric material layer is then etched to providing an opening. In oneembodiment, the opening is a circular, oblong, or other suitablecontact-like opening exposing a portion of top electrode 206. In anotherembodiment, the opening is a trench exposing two or more top electrodes206 along a row or column of the array of memory cells.

A contact material, such as TiN, TaN, TiSiN, TaSiN, TiAlN, WN, or othersuitable contact material is conformally deposited over exposed portionsof the etched first dielectric material layer and the top electrodes206. The contact material layer is deposited using CVD, HDP-CVD, ALD,MOCVD, PVD, JVD, or other suitable deposition technique. A seconddielectric material or semiconducting material, such as SiO₂, SiO_(x),SiN, FSG, BPSG, BSG, low-k material or other suitable dielectric orsemiconducting material is deposited over the contact material layer toprovide a second dielectric material or semiconducting material layer.The second dielectric material or semiconducting material layer isdeposited using CVD, HDP-CVD, ALD, MOCVD, PVD, JVD, or other suitabledeposition technique. The second dielectric material or semiconductingmaterial layer and the contact material layer are then planarized toexpose the first dielectric material layer and to provide contacts 208as previously described and illustrated with reference to FIGS. 3-6.

Embodiments of the present invention provide phase change memory cellsincluding cup-shaped or U-shaped contacts. The cup-shaped or U-shapedcontacts reduce the heat loss from the phase change material duringprogramming of the memory cells. By reducing the heat loss, the contactsreduce the current used to program the memory cells.

While the specific embodiments described herein substantially focused onusing phase change memory elements, the present invention can be appliedto any suitable type of resistive or resistivity changing memoryelements.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

1. An integrated circuit comprising: a bottom electrode; a topelectrode; resistivity changing material between the bottom electrodeand the top electrode; a contact contacting the top electrode, thecontact including a bottom and sidewalls; and first material between thesidewalls of the contact.
 2. The integrated circuit of claim 1, whereinthe first material comprises dielectric material.
 3. The integratedcircuit of claim 1, wherein the first material comprises semiconductingmaterial.
 4. The integrated circuit of claim 1, wherein the contactcomprises a cup-shaped contact.
 5. The integrated circuit of claim 4,wherein the cup-shaped contact has a circular cross-section.
 6. Theintegrated circuit of claim 4, wherein the cup-shaped contact has anoblong cross-section.
 7. The integrated circuit of claim 1, wherein thecontact comprises a U-shaped contact.
 8. The integrated circuit of claim7, wherein the U-shaped contact contacts at least two top electrodes. 9.The integrated circuit of claim 1 wherein the resistivity changingmaterial comprises a phase change material.
 10. A system comprising: ahost; and a memory device communicatively coupled to the host, thememory device including a plurality of memory cells, each memory cellcomprising: a bottom electrode; a top electrode; phase change materialbetween the bottom electrode and the top electrode; a contact contactingthe top electrode, the contact including a bottom and sidewalls; andfirst material between the sidewalls of the contact.
 11. The system ofclaim 10, wherein the first material comprises dielectric material. 12.The system of claim 10, wherein the first material comprisessemiconducting material.
 13. The system of claim 10, wherein eachcontact comprises a cup-shaped contact.
 14. The system of claim 13,wherein each cup-shaped contact has a circular cross-section.
 15. Thesystem of claim 13, wherein each cup-shaped contact has an oblongcross-section.
 16. The system of claim 10, wherein each contactcomprises a U-shaped contact.
 17. The system of claim 16, wherein eachU-shaped contact contacts at least two top electrodes.
 18. The system ofclaim 10, wherein the memory device further comprises: an access devicecoupled to the bottom electrode.
 19. The system of claim 10, wherein thememory device further comprises: a sense circuit configured to read datastored in the phase change material; a write circuit configured to writedata to the phase change material; and a controller configured tocontrol the sense circuit and the write circuit.
 20. A memorycomprising: a bottom electrode; a top electrode; phase change materialbetween the bottom electrode and the top electrode; and means forthermally insulating a top of the top electrode and electricallycoupling the top electrode to upper metallization layers.
 21. The memoryof claim 20, wherein a cross-sectional width of the phase changematerial is greater than a cross-sectional width of the bottomelectrode.
 22. The memory of claim 20, wherein a cross-sectional widthof the phase change material is less than a cross-sectional width of thebottom electrode.
 23. The memory of claim 20, wherein the phase changematerial comprises a tapered portion.
 24. The memory of claim 20,wherein the means for thermally insulating the top electrode andelectrically coupling the top electrode to upper metallization layers iscentered over the top electrode.
 25. A method for fabricating anintegrated circuit having a memory cell, the method comprising:providing a bottom electrode, a phase change material storage locationover the bottom electrode, and a top electrode over the phase changematerial storage location; depositing a first dielectric material layerover the top electrode; etching the first dielectric material layer toform an opening exposing a portion of the top electrode; conformallydepositing a contact material layer over exposed portions of the topelectrode and etched first dielectric material layer; depositing asecond material layer over the contact material layer; and planarizingthe second material layer and the contact material layer to expose theetched first dielectric material layer to provide a contact.
 26. Themethod of claim 25, wherein depositing the second material layercomprises depositing a second dielectric material layer.
 27. The methodof claim 25, wherein depositing the second material layer comprisesdepositing a semiconducting material layer.
 28. The method of claim 25,wherein etching the first dielectric material layer comprises etchingthe first dielectric material layer to form a contact-like opening. 29.The method of claim 25, wherein etching the first dielectric materiallayer comprises etching the first dielectric material layer to form atrench opening.
 30. The method of claim 25, wherein providing the phasechange material storage location comprises providing a pore phase changematerial storage location.
 31. The method of claim 25, wherein providingthe phase change material storage location comprises providing amushroom phase change material storage location.
 32. A method forfabricating a memory, the method comprising: providing a plurality ofbottom electrodes; providing a phase change material storage locationover each bottom electrode; providing a top electrode over each phasechange material storage location; depositing a first dielectric materiallayer over the top electrodes; etching the first dielectric materiallayer to form trenches exposing a portion of each top electrode alongeach trench; conformally depositing a contact material layer overexposed portions of the top electrodes and etched first dielectricmaterial layer; depositing a second material layer over the contactmaterial layer; and planarizing the second material layer and thecontact material layer to expose the etched first dielectric materiallayer to provide U-shaped contacts.
 33. The method of claim 32, whereindepositing the second material layer comprises depositing a seconddielectric material layer.
 34. The method of claim 32, whereindepositing the second material layer comprises depositing asemiconducting material layer.
 35. The method of claim 32, whereinproviding the phase change material storage locations comprisesproviding pore phase change material storage locations.
 36. The methodof claim 32, wherein providing the phase change material storagelocations comprises providing mushroom phase change material storagelocations.